Exemplary embodiments of the present invention relate to a technology for fabricating a semiconductor device, and more particularly, to a method for forming an isolation layer of a semiconductor device.
A Shallow Trench Isolation (STI) process is currently used to form trenches in a substrate to define active regions of a semiconductor device and to form an isolation layer by filling the trenches with an insulation layer.
A high-density plasma (HDP) oxide layer, a spin-on-dielectric (SOD) oxide layer, or a stacked structure of an SOD oxide layer and an HDP oxide layer may be used as the insulation layer filling the trenches.
However, as semiconductor devices continue to be highly integrated, a void or seam may occur in the HDP oxide layer. Also, as the active region is reduced, margins of error for subsequent processes (e.g., margins of error for gap-filling trenches for forming an isolation layer) become insufficient, and as a result, memory refresh period is reduced as well due to self-aligned contact failure and leakage current from a substrate. Moreover, while a deposition process and an etch process are repeated to deposit the HDP oxide layer, a liner oxide layer does not sufficiently protect a liner nitride layer, and as a result, some of the liner nitride layer is lost. Such a loss may, lead to liner nitride layer clipping at active corners.
On the other hand, the SOD oxide layer is advantageous in that the SOD oxide layer has an excellent gap-fill characteristic because it is formed through a coating process.
The SOD oxide layer, however, has high permeability and fast wet etch rate, which are disadvantageous characteristics.
To cure the SOD oxide layer and make the layer quality hard, an annealing process is performed after the formation of the SOD oxide layer. After the annealing process, wide areas are cured and the layer quality of the SOD oxide layer becomes harder, but portions filling the trenches remain uncured. Also, in narrow areas, the extent of curing differs according to the depth of a trench, and the SOD oxide layer shrinks as it is cured.
Since the layer quality differs depending on the annealing conditions, it is difficult to use the SOD oxide layer. For example, the SOD oxide layer is not completely cured in a narrow area, and thus, out-gassing occurs continuously during a subsequent thermal treatment and the out-gassing changes the layer quality. Since the layer quality is changed, the etch rate may become different and defects may be caused. Also, since there are differences in the shrinkage of the SOD oxide layer and stress-related changes as a result of the annealing process, a crack may occur at the boundary between the SOD oxide layer and a peripheral layer.